Semiconductor integrated circuits are quickly destroyed when subjected to excessive voltages. One of the most common causes of damage is electrostatic discharge or ESD. An ESD event occurs whenever a packaged IC is subjected to the dissipation of static electricity, which may occur whenever the pins of the IC come into contact with another surface. Thus, the likelihood of an ESD event damaging or destroying an IC is substantial during packaging and handling of the IC. Even after an integrated circuit is mounted on a circuit board and housed within a system, such as a modem or PC, it is nonetheless susceptible to ESD events discharging in and around the circuitry.
The human body is a major source of static charge. It is sometimes modeled as a 100 picofarad capacitor, capable of storing two or three kilovolts and having a series resistance on the order of a few K-ohms. Thus, when the pins of a packaged integrated circuit are touched by a person, a peak current on the order of two amperes can be delivered through the MOS devices on the IC. These voltages and currents can easily damage or destroy the gate oxides of modem MOS devices on the IC which have sub-micron geometries. To address this problem, most ICs are provided with some sort of ESD protection scheme.
Frequently, ESD protection schemes comprise one or more diodes or SCR circuits coupled between each input/output (I/O) pad on the chip, and the power supply rails. When an excessive voltage appears at the corresponding pin, for example an ESD event, the diode, SCR or similar circuitry turns on very quickly, to short the high voltage to the power supply node. For example, U.S. Pat. Nos. 4,829,350; 4,811,155; 4,855,620; and 4,692,834 all disclose ESD protection circuits in which the channel of an MOS device is coupled between ground and a pin of the IC. Such an MOS device has a parasitic bipolar transistor coupled in parallel with the MOS device. When a positive ESD event occurs at the pin, the bipolar transistor is forward-activated, and a substantial portion of the ESD current is passed through it to ground. An electrostatic discharge protection circuit having a non-lightly doped drain MOS device for protecting other lightly doped drain devices is disclosed in U.S. Pat. No. 5,246,872. A method for forming a silicon-controlled rectifier (SCR) in a semiconductor integrated circuit is described in U.S. Pat. No. 5,369,041. Another CMOS on-chip ESD protection circuit and related semiconductor structure are shown in U.S. Pat. No. 5,182,220.
What is lacking, however, is a means for meaningfully comparing these various protection schemes and their effectiveness relative to a given semiconductor process. In other words, there are no standards for comparing the effectiveness of various alternative ESD protection structures or designs. In the prior art, a semiconductor manufacturer implements an ESD protection scheme onto a product design. The product design goes through the usual floor planning, placement, routing, and other design steps which are well-known in the semiconductor industry. After the design is completed, the circuit is fabricated according to the manufacturer's standard process, and then samples devices are tested. Typically, they are first tested to insure functionality, and then they are submitted for ESD testing or "zapping." The devices are subjected to various ESD zap voltages (for example at 1 kV, 1.5 kV and 2 kV) and various power and ground configurations. The core functionality is confirmed once again after the zapping is completed. The highest zap voltage for which the core maintained functionality post-ESD zap are reported as the ESD voltage performance of the product.
This prior art methodology has several disadvantages. First, in the prior art methodologies, the ESD circuits are connected to the chip internal circuits or "core." Often, manufacturing variations in the core and the core circuitry itself can affect the results of the ESD protection testing. Second, these tests are not very accurate because of the granularity of the ESD testing voltages. Finer variations in ESD test voltages might be applied, but that approach severely impacts testing time. A third disadvantage of the prior art is that feedback on ESD structure design is very slow because the typical design, manufacturing and testing cycle often takes 15-20 weeks. Each iteration required to test an alternative protection scheme is very time consuming and expensive.